Most multiprocessor systems have two or more processors that are not completely identical, but instead have a degree of individual special features and functions. The tighter coupling between the multiprocessors integrated on a single chip allows for a more efficient passing of data than for similar multiprocessors implemented at the board level. Each processor may have a different memory map, different peripheral set and perhaps even a different instruction set. In applications that have very distinct boundaries, such as a cell phone, this method of extracting optimum performance is crucial.
It is desirable to define an architecture that offers the modularity and flexibility that the multiprocessor system offers and reuse advantages of a single processor system, but also the lower development costs and scalability. The symmetric parallel processing system, upon which this invention is based, was developed for this reason.
One of the more formidable difficulties designers of any symmetric multiprocessing system (SMP) must deal with is the issue of data coherence. Since all central processing units have access to all system resources such as memory and peripherals, if one central processing unit changes a value in memory, it must not affect the operation of the other central processing units. As an example, if a shared variable exists in memory that is used as a lock variable with an active locked state signified by a logical ‘1’, no other central processing unit can use the process associated with the lock until it is first set to logical ‘0’ by the lock-grabbing central processing unit. For example, suppose central processing unit 101 reads the lock variable, checks the value and then proceeds to set the lock. However, central processing unit 103 also reads the lock before central processing unit 101 has completed setting the lock. Both central processing units proceed under the assumption that the lock is not set. They both proceed with the process that the lock is designed to safeguard against. This will cause program behavior that was not anticipated by the software engineer and can cause an application to perform differently than expected.
Many desktop central processing units avoid this unwanted occurrence by having this special lock-set/lock reset hardware primitive as part of the instruction set. For example, the base central processing unit used in the symmetrical multiprocessor system will have a special instruction or instruction pair that will check memory and set a lock flag bit if that location is not set. This atomic operation is not interruptible and it thereby insures that another central processing unit cannot read the same location before the first central processing unit has completed writing the set value back to memory. This approach is not available to the base central processing unit of an embedded multiprocessor if this instruction is not a part of the original instruction set.